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ID:1701698
User:71.138.23.59
Article:Multi-core processor
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(Undid revision 594853680 by 163.6.214.117 (talk) - rv damage)
(Softened jargon with a lazy hyperlink. ("ILP" needs work) --~~~~Doug Bashford)
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* For general-purpose processors, much of the motivation for multi-core processors comes from greatly diminished gains in processor performance from increasing the [[frequency scaling|operating frequency]]. This is due to three primary factors:
 
* For general-purpose processors, much of the motivation for multi-core processors comes from greatly diminished gains in processor performance from increasing the [[frequency scaling|operating frequency]]. This is due to three primary factors:
 
*# The ''memory wall''; the increasing gap between processor and memory speeds. This effect pushes cache sizes larger in order to mask the latency of memory. This helps only to the extent that memory bandwidth is not the bottleneck in performance.
 
*# The ''memory wall''; the increasing gap between processor and memory speeds. This effect pushes cache sizes larger in order to mask the latency of memory. This helps only to the extent that memory bandwidth is not the bottleneck in performance.
*# The ''ILP wall''; the increasing difficulty of finding enough parallelism in a single instructions stream to keep a high-performance single-core processor busy.
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*# The ''ILP wall'', (or wall of [[instruction-level parallelism]]); the increasing difficulty of finding enough parallelism in a single instructions stream to keep a high-performance single-core processor <!-- ...in a parallel array...? --> busy.
 
*# The ''power wall''; the trend of consuming exponentially increasing power with each factorial increase of operating frequency. This increase can be mitigated by "[[Die shrink|shrinking]]" the processor by using smaller traces for the same logic. The ''power wall'' poses manufacturing, system design and deployment problems that have not been justified in the face of the diminished gains in performance due to the ''memory wall'' and ''ILP wall''.
 
*# The ''power wall''; the trend of consuming exponentially increasing power with each factorial increase of operating frequency. This increase can be mitigated by "[[Die shrink|shrinking]]" the processor by using smaller traces for the same logic. The ''power wall'' poses manufacturing, system design and deployment problems that have not been justified in the face of the diminished gains in performance due to the ''memory wall'' and ''ILP wall''.
   
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